Embodiments of the present invention relate to generating clock signals in electronic systems.
The duty cycle of an oscillating clock signal is generally understood to refer to or describe a ratio of the time that the signal is in a high state to the total period of the signal. Duty cycles are typically expressed as a percentage. Clock signals can be generated in a wide variety of well known ways, including, for example, crystal oscillators, resistor-capacitor (RC) oscillators, ceramic resonators and the like.
Much digital circuitry, for example, high performance digital circuitry, requires a very specific duty cycle from an input clock source. For example, many microprocessors and analog to digital converters require an input clock source with a duty cycle of 50 percent. Typically, the input duty cycle is required to be within a few percent, e.g., two percent, of this nominal value. Some circuits, for example semiconductor memory devices, require a duty cycle that is substantially not 50 percent.
It is frequently the case that a clock signal with an acceptable duty cycle is not available within a circuit design. Often, clock sources with required precision are undesirably expensive in terms of acquisition cost and/or area requirements if they are available. Consequently, it is frequently necessary to condition and/or adjust a clock signal in order to produce a new signal with desirable duty cycle characteristics.
Conventionally, a phase locked loop is used to generate a 50 percent duty cycle. Such phase locked loops generally have undesirable power consumption. Further, phase locked loops typically are relatively large circuits and require a high degree of skill to design. Additionally, phase locked loops have not been conventionally used to produce duty cycles of other than 50 percent.
Consequently, a clock generator capable of generating clock signals having desirable duty cycle characteristics at low power consumption and with relatively small area requirements is highly desirable.
A system and method of generating a clock are disclosed. A first clock is accessed. A delayed version of the first clock is created. A second clock signal is generated. A first edge of the second clock signal corresponds to a transition of the first clock signal, and a second edge of the second clock signal corresponds to a transition of the delayed version of the first clock signal.